The use of hierarchical structures for design of high-speed digital comparators on FPGA/SoC

Valery Salauyou

Abstract

n/a
Author Valery Salauyou (FCS / DDMCG)
Valery Salauyou,,
- Department of Digital Media and Computer Graphics
Journal seriesMeasurement Automation Monitoring, [Pomiary Automatyka Kontrola], ISSN 2450-2855, [0032-4140], (B 11 pkt)
Issue year2016
Vol62
No6
Pages196-198
URL http://pak.info.pl/index.php?menu=artykulSzczegol&idArtykul=4588
Internal identifier000038585
Languageen angielski
LicenseJournal (articles only); published final; ; with publication
Score (nominal)11
Score sourcejournalList
ScoreBUT score = 11.0, 27-12-2018, manual
Ministerial score = 11.0, 20-01-2020, ArticleFromJournal
Ministerial score (2013-2016) = 11.0, 20-01-2020, ArticleFromJournal
Citation count*
Cite
Share Share

Get link to the record


* presented citation count is obtained through Internet information analysis and it is close to the number calculated by the Publish or Perish system.
Back
Confirmation
Are you sure?