Balanced Power, Speed and Area Minimization of Finite State Machines for FPGA Devices

Adam Klimowicz


A balanced method for the minimization of incompletely specified finite state machines (FSMs) implemented on Field Programmable Logic Devices (FPGA) is proposed. In this method, such optimization criteria as the power consumption, speed of operation and device area are taken into account already at the stage of minimizing internal states. The method also takes into consideration the technological features of programmable logic and the state encoding method. The method is based on sequential merging of two internal states. For this purpose, the set of all pairs of states that can be merged is found, and the pair of states that has the highest rank is chosen for merging. The rank is calculated on the base of estimations of power, speed and area parameters and the user is able to choose the direction of minimization by setting weights for each criteria. In addition, the proposed method allows to minimize the number of transitions and redundant input variables of the FSM. Algorithms for the estimation of optimization criteria values are described and experimental results are also discussed.
Author Adam Klimowicz (FCS / DDMCG)
Adam Klimowicz,,
- Department of Digital Media and Computer Graphics
Publication size in sheets0.55
Book Saeed Khalid, Rituparna Chaki, Janev Valentina (eds.): Computer Information Systems and Industrial Management : 18th International Conference : CISIM 2019 : proceedings, Lecture Notes In Computer Science, no. 11703, 2019, Springer, ISBN 978-3-030-28956-0, 540 p., DOI:10.1007/978-3-030-28957-7
Keywords in EnglishFinite state machines Logic synthesis Speed optimization Power optimization Area optimization FPGA
Internal identifierROC 19-20
Languageen angielski
Score (nominal)40
Score sourceconferenceList
ScoreMinisterial score = 40.0, 09-03-2020, ChapterFromConference
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