Two FPGA Devices in the Problem of Finding Minimal Reducts

Mateusz Choromański , Tomasz Grześ , Piotr Hońko

Abstract

Speeding up attribute reduction process is an important issue in data mining. The goal of this paper is to compare two hardware implementations of minimal reducts computation, i.e. the previously introduced implementation on Intel Arria V SoC and a newly proposed solution on Xilinx Zynq Ultrascale+ MPSoC. Two versions of an attribute reduction algorithm, i.e. blind and frequency based breadth search strategies, were implemented on the two frameworks. Experimental research showed that finding minimal reducts can be accelerated several times when using the new device.
Author Mateusz Choromański (FCS / DISCN)
Mateusz Choromański,,
- Department of Information Systems and Computer Networks
, Tomasz Grześ (FCS / DISCN)
Tomasz Grześ,,
- Department of Information Systems and Computer Networks
, Piotr Hońko (FCS / DISCN)
Piotr Hońko,,
- Department of Information Systems and Computer Networks
Pages410-420
Publication size in sheets0.5
Book Saeed Khalid, Rituparna Chaki, Janev Valentina (eds.): Computer Information Systems and Industrial Management : 18th International Conference : CISIM 2019 : proceedings, Lecture Notes In Computer Science, no. 11703, 2019, Springer, ISBN 978-3-030-28956-0, 540 p., DOI:10.1007/978-3-030-28957-7
Keywords in EnglishAttribute reduction Minimal reducts Breadth search strategy Hardware implementation Field programmable gate arrays
DOIDOI:10.1007/978-3-030-28957-7_34
Internal identifierROC 19-20
Languageen angielski
Score (nominal)40
Score sourceconferenceList
ScoreMinisterial score = 40.0, 30-03-2020, ChapterFromConference
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